| 摘要 |
PURPOSE:To reduce the cost by adopting a digital circuit for each section so as to prevent the effect of external environment and simplifying the configuration. CONSTITUTION:A timing of reception data S is fed to a phase comparator circuit 12, in which the timing signal is compared with a clock pulse QD fed from a 1/16 frequency division counter 16, and the result is fed to a phase adjustment circuit 17. When the reference clock pulse K2, that is, the timing of the clock pulse QD is led, a count stop signal EP is fed to the counter 16, then the phase of the clock pulse QD is delayed by a prescribed quantity. When the timing of the reference clock pulse K2 is lagged, an inverting signal H is fed to a selector 15 and the count of the clock pulse K4 being the reference of the clock pulse QD is quickened. Then the phase of the clock pulse QD is led. Each section consists of a digital circuit and the external effect is prevented. |
