INTEGRATED CMOS SEMICONDUCTOR CIRCUIT

摘要

An integrated CMOS semiconductor circuit to reduce power consumption in which at least one transistor pair can be operated stably at different supply voltage in that each supply voltage is allocated a threshold voltages which is adjustable via the trough and substrate bias voltages. The substrate of the transistor pair is connected to a substrate bias voltage generator circuit and the trough to a trough bias voltage generator circuit which, dependently upon an input signal representing the height of the supply voltage, sets the height of the bias voltage corresponding to the supply voltage in order to match the threshold voltage to the supply voltage concerned in such a way that the stable operation of the transistor pair is ensured at all times. A data processing system associated to the integrated semiconductor circuit, which, for example, operates at a supply voltage of 3.6 V, a clock frequency of 66 MHz and a relative power consumption of 1, after switching over to a supply voltage of 1.2 V and a clock frequency of below 5 MHz/attains a power consumption of less than 0.01 and an approximately hundredfold increase in the running time for a battery-operated PC.