| 摘要 |
<p>Integrated CMOS static RAM having a hierarchical and modular architecture where memory cell pairs (10) are the basic elements of the hierarchy and are organized in N pair structures forming a second hierarchical level: each cell pair has write control lines (W1,W2), one per each cell, separate from a read control line (RC) common to both cells and a bit write line common to both cells and separate from two bit read lines (BR1,BR2) one per each cell. In the N pair structure the bit write lines of the cells are coupled together to form a bit write distributor (BWD) and the two bit read lines of each cell pair are respectively coupled with the corresponding bit read lines of the other cell pairs to form two separate partial bit read collectors selectively coupled through buffers (12,13) and control gates (14,15) to a full bit read collector (BC). Separation of the read/write paths for both data and conrol allows for a hierarchical architecture with multiple selection levels, substantive reduction of the loads driven at the several levels, which loads may be predetermined and bring up to performances substantially independent of the RAM size. <IMAGE></p> |
