发明名称 Method for testing semiconductor integrated circuits soldered to boards and use of a transistor tester for this method
摘要 A method for testing a semiconductor integrated circuit soldered into a printed circuit board makes use of the existence of parasitic transistors which occur on integrated circuits having diodes formed thereon. The method includes applying a voltage across the pins of the integrated circuit to be tested, measuring currents resulting from the voltage applied across the pins of the integrated circuit, connecting a transistor tester to selected pins of the integrated circuit, and determining typical control or switching characteristics of a parasitic transistor (1T, 2T) of the semiconducting integrated circuit (IC1, IC2). A commercial transistor tester is usable to perform the method.
申请公布号 US5280237(A) 申请公布日期 1994.01.18
申请号 US19920855666 申请日期 1992.03.23
申请人 ITA INGB TESTAUFGABEN 发明人 BUKS, MANFRED
分类号 G01R31/04;G01R31/28;G01R31/316;(IPC1-7):G01R31/00 主分类号 G01R31/04
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