| 摘要 |
PURPOSE:To easily confirm the operation of a shift register as a parallel/serial data conversion circuit constituting a data synchronizer block. CONSTITUTION:One input terminal D5 among parallel data input terminals D0-D7 is used as an input terminal for a test, the input terminal D5 for a test is connected with a shift input terminal SR, data in more than a prescribed level are supplied to the input terminal D5 for a test, and then clock pulses Cp in a number corresponding to the number of the parallel data input terminals D0-D7 are supplied to a clock pulse input terminal CLK. Thus, the level of data appearing at a serial data output terminal Q5 is compared with the level of the data supplied to the input terminal D5 for a test after the clock pulses Cp are supplied, so that the operation of a shift register 30 can easily be confirmed. When the level of the data appearing at the serial data output terminal Q7 is the same as the level of the data supplied to the input terminal D5 for a test as the result of a level comparison, the shift register 30 can be correctly operated. |
