发明名称 ADDITION VERIFYING METHOD FOR PIN SCAN-IN CIRCUIT
摘要 PURPOSE:To efficiently verify the addition of a pin scan-in circuit without uselessness. CONSTITUTION:The pin scan-in circuit is retrieved from circuit information, and linked pin information is detected (a). Next, net information linking an output pin is retrieved from the linked pin information (b) and the linked pin information is retrieved from the retrieved net information (c). Afterwards, circuit information linking an input pin is retrieved from the retrieved pin information (d) and next, forward trace is repeated until reaching an LSI output pin from the retrieved circuit information so as to discriminate the arrived LSI output pin (e).
申请公布号 JPH064339(A) 申请公布日期 1994.01.14
申请号 JP19920163281 申请日期 1992.06.23
申请人 FUJITSU LTD 发明人 NAGAKURA MIEKO
分类号 G06F11/22 主分类号 G06F11/22
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