| 摘要 |
PURPOSE:To enable the surface area of a lower electrode of a capacitor to be increased easily and efficiently to thereby increase a storage capacitance of a DRAM cell having a layered capacitor. CONSTITUTION:After a polycrystalline silicon film 1 containing phosphorus and a first amorphous silicon film 2 are layered, they are patterned into a desired electrode shape. Then, a second amorphous silicon film 3 is deposited, and left on only a side wall portion of the layered pattern by anisotropic etching. Then, short-time annealing is performed at a high temperature in a reduced- pressure atmosphere to cause minute silicon crystal grains to grow on the amorphous silicon film. Phosphorus diffuses from the polycrystalline silicon film 1 into the surface-covering amorphous silicon films 2 and 3 by a heat treatment in a subsequent manufacturing step, to complete a lower electrode 5 the whole of which is doped into an n-type. |
