发明名称 SIGNAL MULTIPLEXING AND DEMULTIPLEXING CIRCUIT
摘要 <p>PURPOSE:To eliminate a bottle neck without giving a large revision in the inside of the circuit at a low cost between synchronization circuits with respect to the signal multiplexing and demultiplexing circuit. CONSTITUTION:The signal multiplexing and demultiplexing circuit consists of a signal multiplexing circuit 28 multiplexing signals a, b from a synchronization circuit 23, 1st-4th flip-flop circuits 29-32 and a changeover circuit 33 and a signal demultiplexing circuit 36 comprising 5th-8th flip-flop circuits 39-42 demultiplexing the multiplexed signal which are provided between synchronization circuits 23, 37 of LSIs 21, 22.</p>
申请公布号 JPH066334(A) 申请公布日期 1994.01.14
申请号 JP19920163282 申请日期 1992.06.23
申请人 FUJITSU LTD 发明人 RIKA SHIN
分类号 H04J3/00;H04L7/00;(IPC1-7):H04L7/00 主分类号 H04J3/00
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