| 摘要 |
PURPOSE:To prevent parity error from being erroneously detected at the time of starting a system by inhibiting the detection of parity error even when data are erroneously read out before a microcomputer writes data in a memory for data just after the system is started. CONSTITUTION:A parity check inhibiting circuit 1 composed of an RS flip-flop 305 and an AND circuit 306 is added for making the result of parity check invalid when no data are written in the memory for data. Assuming that data are erroneously read out without even once writing data and no parity is established between the contents of the memory for data and the contents of a memory for parity, at this time, the number of H adding A-H inputs and an I input is turned to an odd number, and a SIGMAO output 303 is turned to H. Since a parity check start signal is L, however, an AND circuit output 313 appearing in the AND circuit 306 is turned to L, and the microcomputer is not notified parity error. |
