| 摘要 |
PURPOSE:To enable a delay detector to operate with low power consumption even for a signal having a high transmission rate by switching a regenerated clock at the timing of detecting of the initial phase of a data clock by a data clock phase detecting circuit. CONSTITUTION:This detector is equipped with a phase difference detecting means 12 and the initial phase of the data clock is detected by a data clock phase detecting circuit 16 and employed as a trigger signal for initializing reset of the regenerated clock. A 1st clock is used as a sampling clock by the detecting means 12 to perform the A/D conversion of the base band signal and detect the phase difference from data before one time slot interval. At this time, a timing error detecting circuit 14 detects an error in the timing of sampling and a clock phase control circuit 17 corrects the error. Then a switching means 18 switches the 1st clock to the 3rd clock generated by a circuit 17 corresponding to the error detected by the circuit 14. Then high-speed synchronization becomes possible to enable the operation with the low power consumption for the signal which has the high transmission rate. |
