| 摘要 |
PURPOSE:To suppress a decrease of a clock component and sufficiently display the capability for equalization by providing an AGC circuit between a tank circuit and a clock circuit and keeping the output signal level of a clock frequency constant. CONSTITUTION:A decision feedback type equalizer 41 removes an inter-code interference by phasing and multipliers 21 and 22 demodulate Pand Q-channel base band signals with 1st and 2nd orthogonal regenerated carrier signals. Nonlinear circuits 27 and 28 generates clock signals for the signals, the tank circuit 31 extracts a clock frequency component, and a clock synchronizing circuit 12 generates a signal synchronized with the clock frequency. Then A/D converters 29 and 30 convert the demodulated base band signal of the output signal into a digital signal, which is supplied to a decision feedback type equalizer. The AGC circuit 11 is provided between the circuits 31 and 12 to keep the output signal level of the clock frequency constant, and then a clock synchronism losing phenomenon is suppressed to maintain stable equalization characteristics. |
