| 摘要 |
<p>A circuit for controlling the phase of a video signal, wherein control of the phases of a video signal and a sampling clock is performed automatically, and the operability thereof is improved. A delay circuit (24) outputs delayed clocks (DP) whose phases are different from each other. According to switching signals (SS1-SS3) outputted from a control circuit (23), switching circuits (25a-25c) select respectively one of the delayed clocks (DP) having different phases from each other. Counters (28a-28c) count the numbers of pixel data (ED) which are latched by data latching circuits (26a-26c) at every time of output of the delayed clocks (DP) from the corresponding switching circuits (25a-25c). The control circuit (23) confirms these counted values of every picture frame. When all these counted values are respectively the same values or high counted by the counter (28b) in the first sampling picture frame, a switching circuit (25d) is made to select a clock having the same phase as that of the delayed clock (DP) of the switching circuit (25b), and is made to output it to a panel display. <IMAGE></p> |
