| 摘要 |
The device includes a CPU (1) for connecting the data bus to the address bus, a memory device (28) possessing ROM and RAM, a data bus selective output means (5) for selectively outputting the bits of the data bus by the specified address, a user ladder command decoding arithmatic processing means (6) for acting the command decoding and arithmatic, stacks (7,8) for saving or outputting the arithmatic result, a clock generator (9) for driving the result of a ladder command arithmatic processor (27) to the stack, and the ladder command arithmatic processor (27) possessing AND and OR gates.
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