发明名称 Phase lock loop frequency correction circuit
摘要 A phase lock loop circuit (10) which locks to a frequency within a range of input signal frequencies. A frequency discriminator (12) of phase lock loop circuit (10) determines a maximum pulse width of the input signal by counting a number of pulses of a reference signal in each of a series of pulses of the input signal. A coarse frequency controller (16) compares the maximum pulse width to two threshold values to determine whether the reference signal should be coarsely or finely adjusted. If the reference signal is coarsely adjusted, control circuit (16) provides a coarse frequency control signal to indicate whether a voltage controlled oscillator, VCO, (26) should increase or decrease the reference frequency. If the reference frequency is finely adjusted, a phase discriminator (22) provides a fine frequency control signal to the VCO to either increase or decrease the frequency of the reference signal with greater resolution.
申请公布号 US5278874(A) 申请公布日期 1994.01.11
申请号 US19920939745 申请日期 1992.09.02
申请人 MOTOROLA, INC. 发明人 LIU, CLIF;KLOKER, KEVIN L.;WERNIMONT, THOMAS L.
分类号 H03L7/113;H04L7/06;H04L7/10;(IPC1-7):H03D3/24 主分类号 H03L7/113
代理机构 代理人
主权项
地址