| 摘要 |
PURPOSE:To prevent the lowering of the resistance of a diffusion layer by a method wherein an N<+> type diffusion layer region is formed onto a P-type substrate through the implantation of arsenic ions, an inter-layer insulating film is grown, a contact hile is bored, and phosphorus ions are implanted in quantity less than arsenic ions to shape a thin N-type diffusion layer region. CONSTITUTION:Field oxide films 2 and gate oxide films 3 are formed onto a P-type semiconductor substrate 1. Polycrystalline silicon grown on the whole surface on the P-type semiconductor substrate 1 is patterned to shape a gate electrode 4, and the ions of arsenic having a small thermal diffusion coefficient are implanted to form a diffusion-layer wiring region and shallow N<+> diffusion layers 5 as source-drain region in a transistor. An insulating inter-layer oxide film 6 is grown on the whole surface of the substrate 1, a photo-resist 7 is exposed selectively, and the oxide film 6 is etched while using the photo-resist 7 as a mask to bore contact holes 8. The photo-resist 7 is removed and the ions of N-type phosphorus having a large thermal diffusion coefficient are implanted. Phosphorus ions are implanted in quantity less than arsenic ions at that time, and the whole substrate is thermally annealed, thus shaping a thin N-type diffusion layer 19 surrounding the N<+> diffusion layer 5. Accordingly, the resistance of the diffusion layer is lowered, and the junction capacitance of the diffusion layer can be reduced. |
