发明名称
摘要 PURPOSE:To eliminate an excess vacant region and to contrive to reduce the size of a whole chop by a method wherein plural peripheral blocks are ready-registered in advance as a library and peripheral blocks in the optimum configuration are selected from the library according to the size of the internal cell region and the number of peripheral blocks to be needed and are arranged. CONSTITUTION:Lengthwise blocks (peripheral blocks) 12 are selected for the sides X1 and Y1 of an internal cell region 11 and are arranged because peripheral blocks are needed in large numbers in the sides X1 and Y2, while oblong blocks (peripheral blocks) 13 are selected for the sides X2 and Y2 of the internal cell region 11 and are arranged because the number of peripheral blocks to be needed in the sides X2 and Y2 is less. Accordingly, a vacant region is eliminated and the size of the whole chip can be reduced. Moreover, peripheral blocks in several kinds of configurations are ready-prepared in advance in proper steps between the lengthwise blocks 12 and the oblong blocks 13 according to need and when peripheral blocks in the optimum configuration are selected according to a change in the size of the internal cell region and a change in the number of peripheral blocks, the size of the whole chip can be further reduced.
申请公布号 JPH063826(B2) 申请公布日期 1994.01.12
申请号 JP19850085818 申请日期 1985.04.22
申请人 NIPPON ELECTRIC CO 发明人 TAKAGAKI TAKASHI
分类号 H01L21/822;G06F17/50;H01L21/82;H01L27/02;H01L27/04;(IPC1-7):H01L21/82 主分类号 H01L21/822
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