发明名称 |
Integrated circuit with reduced clock skew |
摘要 |
Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.
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申请公布号 |
US5278466(A) |
申请公布日期 |
1994.01.11 |
申请号 |
US19910812182 |
申请日期 |
1991.12.20 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
HONOA, NOBUNIKO;YOSHIDA, TOYOHIKO;SHIMAZU, YUKIHIKO |
分类号 |
G06F1/10;(IPC1-7):H03K19/00;H01L25/00 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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