| 摘要 |
A latch circuit is provided between a column switch connected to the input/output sides for selecting data lines and a tristate buffer connected to the write side of a memory array, or between the column switch and a sense amplifier connected to the readout side of the memory array. The latch circuit has a capacity corresponding to a plurality of data contents in the tristate buffer or the sense amplifier. While data set in a portion of the latch circuit is being output, the next data can be set in another portion of the latch circuit.
|
