| 摘要 |
In a frequency synthesizer, a first, variable frequency divider and a second frequency divider are activated in response to a periodic power activation pulse. The first frequency divider is driven by a voltage-controlled oscillator and the second frequency divider is driven by a reference frequency oscillator. A timing difference between the outputs of the first and second frequency dividers is detected and converted to a frequency-domain control signal for coupling to the voltage-controlled oscillator. Since the timing difference is converted to a frequency domain signal, the VCO is stabilized once there is a substantial frequency match between the first and second frequency dividers. Since the VCO can be stabilized thereafter, the frequency dividers can be deactivated when the detected timing difference is reduced to an acceptable value and are allowed to remain inactive until the synthesizer is activated again by the next activation pulse. |
