| 摘要 |
The invention relates to integrated-circuit memories, and more particularly those which include redundancy circuits with arrays of fuses for storing the addresses of defective memory elements to be replaced by redundancy elements.
<??>The circuit serving for reading the state of the fuse (TGF) includes a current/voltage converter consisting of an inverter (I1) and a transistor (T1). In order to avoid uncertainty in reading the state of the fuse when the latter is an open circuit, at the moment when voltage is reapplied to the circuit, and to avoid a circuit for reapplying voltage, two additional inverters (I3 and I4) are used in series between the output of the first inverter and the gate of the loop-back transistor (T1). These inverters each include two very asymmetric transistors, the asymmetry being exerted in opposite directions for the two inverters.
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