Integrated circuit memory incorporating test programmes - receives external test and clock signals to initiate automatic test of all memory cells

摘要

The memory is integrated with addressing circuits (6,7) which allow high speed testing of all memory cells under conditions of elevated temperature simulating ageing. The circuit is supplied with an external clock signal (H) and a test signal (T) which disables the control register and activates the addressing circuits, allowing the full memory map to be accessed. The tests allow failure of individual memory cells under conditions of ageing to be identified. ADVANTAGE - Ageing tests on integrated circuit memory at higher speed and lower cost than existing routines.