| 摘要 |
A branch logic circuit processes opcodes and responds to early branch and interrupt conditions. The branch logic circuit provides microaddresses based on the processed opcodes to a microcode table lookup RAM (106), which provides a microinstruction corresponding to the provided microaddress. A forced microaddress logic circuit, responding to late branch and interrupt conditions, provides a forced microinstruction. Selection logic is provided to load either the forced microinstruction or the table lookup microinstruction to the microcode register (124) based on a selection signal provided by the forced microaddress logic circuit. In a second selection logic step, the microinstruction in the microcode register may be replaced by a later forced microinstruction. |
