| 摘要 |
<p>A receiver circuit relies on sample data techniques to filter input data signals having a frequency less than a preselected maximum and greater than a preselected minimum. The circuit also rejects a single sine wave cycle. If an input pulse greater than a preselected maximum termination pulse width is encountered during data reception, then reception activity is terminated. The circuit comprises a comparator (12) responsive to differential inputs, a first pair of clocked sample-data counters (16,18) responsive to positive and negative pulses from the comparator and constituting a low-pass filter and a second pair of clocked sample data counters (26,28) responsive to the outputs of the first pair of counters and constituting a high pass filter. Trigger logic responds to a third pulse of the same polarity of a first pulse to provide an output which enables the reception of data. <IMAGE></p> |
