| 摘要 |
A digital signal comparator circuit (15,26) which reduces the time needed for for performing each comparison operation. Inputs (A,B) are for performing each comparison operation. Inputs (A,B) are supplied to hamming distance enhancers (11,12) to form respective code words et least one bit longer than the respective input signals (A,B). A bit comparator (15) compares respective bit locations of the code words to form a plurality of match indicating signals which are supplied in parallel to gating circuitry (26). Due to the increased Hamming distance of the codewords, any mismatch between the original input signals (A,B) results in at least two of the compared bit positions indicating a mismatch. Therefore at least two parallel paths are provided for discharging the input/output capacitance in the system and the result is available after a shorter delay than that required for a single bit mismatch. <IMAGE> |
