Time delay control for serial digital video interface audio receiver buffer.

摘要

A FIFO memory buffer in a serial digital video interface allows improved timing synchronization between video and audio information and eliminates unpleasant sound effects when multiple data samples are skipped or repeated in series. The FIFO receiver buffer (100) receives and outputs data at respective rates. The FIFO's fullness is monitored and maintained, in response to an external signal, to within a specified range deliminted by an upper and a lower threshold. If the FIFO buffer fullness is below the range's lower threshold, then the FIFO's read address pointer is held so that the immediately preceding read-out data element is read out once more. If the FIFO buffer fullness is over the range's upper limit, then the FIFO's write address pointer is held so that the immediately preceding written-in data element is written over once more.