发明名称 |
Spare memory arrangement |
摘要 |
A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU). |
申请公布号 |
US5276834(A) |
申请公布日期 |
1994.01.04 |
申请号 |
US19900621869 |
申请日期 |
1990.12.04 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
MAURITZ, KARL H.;VOSHELL, THOMAS W.;SHAFFER, JAMES M. |
分类号 |
G06F11/10;G11C29/00;(IPC1-7):G06F12/16;G06F12/02 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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