发明名称 |
Data cache management system with test mode using index registers and CAS disable and posted write disable |
摘要 |
A memory controller which can be used with an external tag RAM is disclosed. Existing index registers in the controller serve double duty as buffers for storing tag RAM data during a test mode. Input/output lines for the external tag RAM are coupled to the index registers in addition to being coupled to a comparator for comparison with an external address during normal operation. A buffer is provided so that data from the external address from the CPU can be written through these same tag RAM input/output lines in order to update the tag RAM after a miss. In order to prevent DRAMS from putting data on the memory bus during a cache RAM test, a CAS inhibit signal is provided to the DRAM state machine. Posted writes are also disabled to avoid interference with the address provided to the tag RAM. |
申请公布号 |
US5276833(A) |
申请公布日期 |
1994.01.04 |
申请号 |
US19900544821 |
申请日期 |
1990.07.02 |
申请人 |
CHIPS AND TECHNOLOGIES, INC. |
发明人 |
AUVINEN, STUART T.;NALE, WILLIAM H. |
分类号 |
G06F11/22;G06F12/08;G11C29/52;(IPC1-7):G06F11/22 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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