发明名称 Bus system for information processing system and method of controlling the same
摘要 A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.
申请公布号 US5276818(A) 申请公布日期 1994.01.04
申请号 US19900512810 申请日期 1990.04.20
申请人 HITACHI, LTD. 发明人 OKAZAWA, KOICHI;AOTSU, HIROAKI;KAWAGUCHI, HITOSHI;JIKIHARA, MASAMI;KOBAYASHI, KAZUSHI;KIMURA, KOICHI;MOCHIDA, TETSUYA
分类号 G06F13/28;G06F13/36;G06F13/364;G06F13/42;(IPC1-7):G06F13/00 主分类号 G06F13/28
代理机构 代理人
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