发明名称 Semiconductor memory with reduced peak current
摘要 A semiconductor memory has sense amplifiers coupled to complementary pairs of bit lines. A first switching element couples the sense amplifiers to a first potential, so that the sense amplifiers can bring one bit line in each pair of bit lines from a precharged state to the first potential. A second switching element couples the sense amplifiers to a shunt node. A third switching element couples the shunt node to the first potential. A capacitor capacitively couples the shunt node to a second potential different from the first potential.
申请公布号 US5276645(A) 申请公布日期 1994.01.04
申请号 US19920861950 申请日期 1992.04.02
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 TANAKA, TAKAYUKI;SUYAMA, JUNICHI
分类号 G11C11/41;G11C7/06;G11C11/401;G11C11/409;G11C11/4091;H01L21/8242;H01L27/108;(IPC1-7):G11C7/00 主分类号 G11C11/41
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