发明名称
摘要 PURPOSE:To stably hold information by piling up the following: a gate electrode for a MISFET constituting a flip-flop circuit for a memory cell; a mask, for impurity introduction use, installed at the side of the gate electrode; a resistance element. CONSTITUTION:When a potential at a 'High' level is applied to a conductive layer 7D (gate electrode) for a MISFET Q1 and a potential at a 'Low' level is applied to a conductive layer 7C (gate electrode) for a MISFET Q2, an electric current from a wiring part VCC for power-supply voltage use flows easily in a resistance element 14B (R2). In addition, since the conductive layer 7C and a mask 9 for impurity introduction use shut off an electric field from a drain region 10 for the MISFET Q2, the electric current from the wiring VCC for power-supply voltage use becomes difficult to flow in a resistance element 14B (R1) (self-bias). That is, the resistance elements 14B (R1, R2) change their resistance values by information (voltage) written in a memory cell and can supply the electric current in a direction which clarifies a potential difference of '1' and '0'; accordingly, they can stably hold an electric charge to be used as information.
申请公布号 JPH061822(B2) 申请公布日期 1994.01.05
申请号 JP19890128812 申请日期 1989.05.24
申请人 HITACHI LTD 发明人 IKEDA SHUJI;NAGASAWA KOICHI;MEGURO SATOSHI;YAMAMOTO AKIRA
分类号 H01L27/11;H01L21/8244;H01L27/10 主分类号 H01L27/11
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