Master connected to common bus providing synchronous, contiguous time periods having an instruction followed by data from different time period not immediately contiguous thereto

摘要

In the present invention a digital communication controller for interfacing with a master processor and a synchronous bus having a plurality of slave processors connected thereto is disclosed. The digital communication controller provides synchronous transfer of instruction and data in each microcycle to the bus. However, the data provided in each microcycle is multiplexed such that it is associated with the instruction transmitted previously but not contiguous in time therewith.