发明名称 Semiconductor memory device having a bit line constituted by a semiconductor layer
摘要 A DRAM cell having a bit line constituted by a semiconductor layer. The DRAM cell comprises a semiconductor substrate of a first conductivity type having a main surface, an insulating film formed on the main surface, an opening formed in the insulating film to communicate with the substrate, and a bit line formed by a semiconductor layer of a second conductivity type formed on the insulating film and that portion of the substrate which is exposed through the opening.
申请公布号 US5276343(A) 申请公布日期 1994.01.04
申请号 US19920943144 申请日期 1992.09.10
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KUMAGAI, JUMPEI;SAWADA, SHIZUO
分类号 H01L21/8242;H01L27/108;(IPC1-7):H01L29/78 主分类号 H01L21/8242
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