| 摘要 |
A memory system adapted to receive a radio frequency signal and produce a signal having a frequency related to the frequency of the received signal for an extended, predetermined period of time. The received signal is heterodyned to an intermediate frequency signal. The intermediate frequency signal is sampled and digitized by an analog-to-digital converter. One bit of each digitized sample has a logic state related to the polarity of the intermediate frequency signal. The bits associated with the samples are stored for a time interval beginning at a time the intermediate frequency signal changes polarity with a predetermined sense, i.e. the start of a complete cycle of the signal. A control signal is produced providing an indication of the portion of the bits stored in the shift register at the end of the time interval which is associated with complete cycles of the stored signal and the portion of the stored bits which is associated with an incomplete cycle of the stored signal. In response to the control signal only the portion of the stored data associated with complete cycles of the signal is recycled in the shift register. With such arrangement the recycled data, which is used to generate the signal having extended time duration, is produced with minimum phase discontinuity.
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