| 摘要 |
<p>A rate converter for converting data rate is adapted to hold, at an output clock rate, by using a plurality of latch circuits (2A, 2B, 2C; 12A, 12B, 12C; 22A, 22B, 22A2, 22B2, 22AB, 22BN), respective signals from the output stages of a shift register (1, 11, 21) operative at an input clock rate to multiply, at the output clock rate by using a plurality of multipliers (4A, 4B, 4C; 14A, 14B, 14C; 261, 262, 26N), held signals from the latch circuits by filter coefficients that a plurality of coefficient generators sequentially generate to add the multiplied outputs by using an adder (5, 15, 27) to provide a rate converted output signal. Thus, this rate converter makes it possible to carry out rate conversion by a single digital filter without necessity of digital filters operative at a clock rate of the least common multiple of the input clock rate and the output clock rate. <IMAGE></p> |
