发明名称 |
CMOS logic circuit. |
摘要 |
<p>A CMOS logic circuit with biased inputs to a predetermined logic level, being of a type including at least one signal input (IN) and logic gates (4,5) for handling said signal, further includes a circuit portion (7) which is connected to the signal input (IN), and the equivalent of a high-value resistance effective to bias said input (IN). <IMAGE></p> |
申请公布号 |
EP0575686(A1) |
申请公布日期 |
1993.12.29 |
申请号 |
EP19920830269 |
申请日期 |
1992.05.27 |
申请人 |
CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO |
发明人 |
IMBRUGLIA, ANTONIO;BENENATI, GIOVANNI |
分类号 |
H03K19/0185;H03K19/0948;(IPC1-7):H03K19/018 |
主分类号 |
H03K19/0185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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