发明名称 TIMING COMPONENT EXTRACTING CIRCUIT
摘要 PURPOSE:To reduce the circuit scale, to attain easy mounting with less power consumption and to suppress noise and oscillation by forming an equivalent amplifier circuit and a differential amplifier circuit being analog circuits so as to extract a clock recovery timing component of a received digital signal. CONSTITUTION:An output of an equivalent amplifier circuit and its inverted wave are inputted to terminals 31, 32 and fed to bases of transistors(TRs) Q1, Q2 being components of the equivalent amplifier circuit. Inverted equivalent amplifier waves are extracted from collectors of the TRs Q1, Q2 and fed to bases of the TRs Q3, Q4 being components of an emitter follower differential amplifier circuit. Thus, a timing extracting signal obtained by rectifying full wave of the equivalent amplifier waveforms inverted to each other is obtained at a terminal 35. Thus, a timing signal is extracted by using the differential amplifier circuit and the difference circuit being analog circuits in this way to reduce the circuit scale and power consumption and the mounting of the circuit is facilitated through semiconductor circuit integration and the circuit is made immune to noise or oscillation.
申请公布号 JPH05347613(A) 申请公布日期 1993.12.27
申请号 JP19920155308 申请日期 1992.06.15
申请人 FUJITSU LTD 发明人 HAYASHI AKIHIKO
分类号 H03L7/00;H04L7/027 主分类号 H03L7/00
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