发明名称 MEMORY TESTING SYSTEM
摘要 PURPOSE:To test a memory attached to a main processor without spending time compared with conventional test without imposing a burden on the main processor. CONSTITUTION:A memory test starting address accumulating part ADRREG 8 and a test finishing part 9 accumulate a starting address and an end address instructed from a CPU 1, respectively. A test address generating part 10 updates successively an address from the start address, and supplies it to a memory part 14. A test data generating part 7 generates write data and supplies the data to an MEM 14 and a test end detecting part 11 compares a memory access address with the end address, and finishes the sequence, in the case they coincide with each other. A data comparing part 16 reads out the data from the starting address after the sequence is finished and compares the data with the data generated by the same sequence. A non-coincidence information accumulating part 17 accumulates the address and the data and notifies them to the CPU 1, in the case the data are in discordance and notifies the normal end information to the CPU 1 in the case all addresses are finished normally.
申请公布号 JPH05342111(A) 申请公布日期 1993.12.24
申请号 JP19920146134 申请日期 1992.06.08
申请人 NEC CORP 发明人 YAMAZAKI SADAO
分类号 G06F11/00;G06F11/22;G06F12/16 主分类号 G06F11/00
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