发明名称 PHASE COMPARATOR CIRCUIT
摘要 PURPOSE:To accurately detect a phase error between a clock pit signal and a clock signal even when a level of an RF signal reproduced from a magneto- optical disk is fluctuated or an optical MTF is fluctuated. CONSTITUTION:A sample-and-hold circuit 4 samples and holds a differentiated, signal (b) resulting from differentiating a clock pit signal (a) by a differentiation device 3 at an edge c1 at a prescribed timing of the clock signal generated by a PLL circuit 5. A detection circuit 12 detects a tilt in the differentiated signal (b) outputted from the differentiation device 3 and outputs a detected tilt alphai to a divider 11. The divider 11 divides a level phii at a prescribed timing of the differentiated signal (b) outputted from the sample-and-hold circuit 4 with the tilt alphai outputted from a sample-and-hold circuit 22 and outputs the quotient to the PLL circuit 5. The PLL circuit 5 generates the clock signal corresponding to the signal inputted from the divider 11.
申请公布号 JPH05343988(A) 申请公布日期 1993.12.24
申请号 JP19920174963 申请日期 1992.06.09
申请人 SONY CORP 发明人 SHIMIZU YASUNARI
分类号 G11B7/00;G11B7/005;G11B11/10;G11B11/105;G11B20/14;H03K5/26;H03L7/085 主分类号 G11B7/00
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