| 摘要 |
PURPOSE:To achieve a prevention of erroneous detection of an address mark or the like by making a second synchronous signal contain none of the shortest inversion pattern continuing from the first synchronous signal containing the shortest inversion pattern in a digital modulation rule. CONSTITUTION:An input data DTi is inputted sequentially into a shift register SR synchronizing a clock CKr and data to be applied to one input terminal of AND circuits AN1-AN16 changes every time each CKr is outputted. On the other hand, an address mark(AM) containing none of the shortest inversion pattern in a digital modulation rule is applied to the other input terminal of the AN1-AN16 from an address mark pattern memory PM. Then, the number of the AN circuits where the outputs of the AN1-AN16 are at an logical H level is counted with a coincidence number counter CT. When the number of coincidences is 16, an AM detection signal DTam is outputted from a comparator CM thereby reducing probability of erroneous detection of the AM. |
