| 摘要 |
The controller improves an effectiveness of RAM with a preset functions. The device includes a synchronous counter (1) for inputting the address of the row and column, a 1st 3-phase buffer (3) for buffering the row address, a 2nd 3-phase inverter (6) for outputting the voltage (VDD) by the control of WE (write enable), a 1st 3-phase inverter (5) for outputting the data in a ROM, an adder (2) for adding the column address and the output address of the 1st 3-phase inverter, and the 2nd 3-phase buffer for outputting the column address. The device controls the read/write address of the RAM.
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