| 摘要 |
PURPOSE:To reduce a parasitic inductance and a parasitic capacitance between a wiring pattern for a high-speed chip and a wiring pattern on an insulating substrate for package use and to connect the high-speed chip to the insulating substrate for package use without spoiling the high-speed performance of the high-speed chip. CONSTITUTION:A chip-mounted package in which a chip 4 has been mounted is constituted in the following manner: a wiring pattern 2 is formed on an insulating substrate 1; a groove 3 is formed on the side on which the wiring pattern 2 on the insulating substrate has been formed in such a way that one part of the wiring pattern 2 is exposed on the insulating substrate 1; the chip 4 is buried inside the groove 3 in such a way that a wiring pattern 5 for the chip 4 is situated on the side of the wiring pattern 2 on the insulating substrate 1; and the wiring pattern 2 on the insulating substrate 1 is connected to the wiring pattern 5 for the chip 4.
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