发明名称 DATA TRANSFER DEVICE AND PARALLEL PROCESSING SYSTEM
摘要 PURPOSE:To realize packet transfer even when a lot of packets having various lengths are mixed, and to perform broadcast transfer at high speed as well by buffering a memory read request in an external memory in the case of disabling a quick response to the request, reading the request when the response is enabled, decoding it and starting a response sequence. CONSTITUTION:The read request of a memory 2 comes from another processor through a network port 4. This request is stored in a buffer 5a and afterwards, it is passed through a selector 16a and decoded by a decode judging means 6. When the quick response to the request is enabled in this case, the memory 2 is read and data are transmitted through a buffer 5b to the network port 4. When the quick response is disabled, the request is temporarily stored in the memory, and the contents are held in a request holding means 17. When the response is enabled later, a data transfer device 1 reads the request stored in the memory 2 and simultaneously cancels the storage of the request.
申请公布号 JPH05342173(A) 申请公布日期 1993.12.24
申请号 JP19920330168 申请日期 1992.12.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OKABAYASHI ICHIRO
分类号 G06F15/17;G06F15/16;G06F15/163;G06F15/173 主分类号 G06F15/17
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