| 摘要 |
PURPOSE:To accelerate speed for transferring data among parallel processors and to accelerate entire processing speed by performing reversible compression and reversible extension to character data and vector data and performing irreversible compression and irreversible extension to the data of still pictures and the data of moving images. CONSTITUTION:The parallel processors can be operated singly as well but are functioned while being mutually connected by link interfaces 3. The link interfaces 3 in four directions are provided and communicated with the four parallel processors. In this case, when data to be transmitted are character or vector data, a data identification flag is turned to '0' and the data are transmitted after being reversibly compressed at a reversible compression/ extension circuit 13. When the data are still picture data or moving image data, the data identification flag is turned to '1' and the data are transmitted after being irreversibly compressed at an irreversible compression/extension circuit 14. Corresponding to whether the received data identification flag is '0' or '1', the parallel processors on the reception side reversibly extend the data at the circuit 13 or irreversibly extend them at the circuit 14. |
