| 摘要 |
PURPOSE:To provide a watchdog timer circuit with simple configuration. CONSTITUTION:A first timer circuit 17 regulating the allowable upper limit time of an output interval between first and second command signals outputted from a CPU 1, second timer circuit 17 regulating the abnormal lower limit time of a cycle for repeating these command signals, and third timer circuit 18 regulating the allowable upper limit time of the cycle for repeating the command signals are serially connected and when the second command signal is outputted before the time-up of the first timer circuit 15 to be started at the time of outputting the first command signal, an enable signal (h) is outputted so as to start the second timer circuit 17. Based on the output of this second timer circuit 17, the third timer circuit 18 is started, and a signal showing the normal state of the CPU 1 is outputted. When the regulated time of the second timer circuit 17 is finished at the time of outputting the enable signal (h) in the next cycle, the second timer circuit 17 is restarted, and the regulated time of the third timer circuit 18 is updated. |
