发明名称 SYSTEM FOR AIDING DEBUGGING OF INTEGRATED CIRCUIT MICROPROCESSOR
摘要 In the system, a machine instruction fetched by an instruction fetching unit (3) is transferred to an instruction recognizing unit (6) as well as to an instruction decoding unit (4). The instruction recognizing unit (6) judges whether or not the operation-code part of the transferred machine instruction is the operation-code to generate a break operation. When an affirmative decision is made, the instruction decoding unit (4) is informed of the message to that effect. The instruction decoding unit (4) transfers a predefined decode result instructing the break operation instead of the decode result of the fetched instruction to an instruction executing unit (5). Thereby, the break operation is started by the instruction executing unit. Therefore, without sensing the address generated with the execution of the instruction, a break is caused at the time intended by the program, and the debugging can be performed.
申请公布号 WO9325967(A1) 申请公布日期 1993.12.23
申请号 WO1992JP00743 申请日期 1992.06.08
申请人 V.M. TECHNOLOGY CORP. 发明人 MATSUMOTO, YUUKOU
分类号 G06F11/00;G06F11/36;(IPC1-7):G06F11/28 主分类号 G06F11/00
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