Clock signal equalisation circuit for data processing system - uses shift registers for controlled shifting of clock signals for different system compensate to obtain synchronisation

摘要

The equalisation circuitry synchronises the individual clock signals (CK1, CK2), for the different components (CH1, CH2) of the data processing system, using shift register with controlled flip flops (FF1..FF4) receiving the clock signals coupled via a ring circuit (RS) for data information transfer. A regulated time stage (TU) allows stepped shifting of one clock signals (CK2) relative to the other, with a control unit (CT) used to detect a common shift register condition after each step. The control unit (CT) is coupled to a controller (SP) for the time stage (TU), with the adjusted clock signal set to a mean value between upper and lower limit values for the time range. ADVANTAGE - Synchronisation of individual clock signals without requiring reference clock signal.