Arrangement in data processing system for system initialization and reset.

摘要

In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation (e.g.processing/logging error data) prior to a processor start. One or more reset areas are defined which are initialized /reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause (e.g. power-on) for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.