HIGH SPEED DIFFERENTIAL SENSE AMPLIFIER FOR USE WITH SINGLE TRANSISTOR MEMORY CELLS

摘要

A novel circuit is provided which allows a differential sense amplifier to be utilized in conjunction with a memory array comprised of a plurality of memory cells each containing a single transistor. A differential input signal is applied to the sense amplifier based upon the binary data stored in an addressed memory cell at a rate equal to or greater than the differential input signal available in prior art differential memory cells having two transistors per cell. This is accomplished by precharging the selected bit line and a reference bit line, and then selecting the word line of the memory cell to be read, while causing the reference memory cell to conduct. The differential voltage between the selected bit line and the reference bit line is then sensed to determine the state of the data stored in the selected memory cell. The ratio of currents through the selected bit line and the reference bit line is selected to be other than one, in order to achieve a rapid differential voltage swing, and that rapid reading of the data stored within the selected memory cell.