A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.
申请公布号
US5272729(A)
申请公布日期
1993.12.21
申请号
US19910763510
申请日期
1991.09.20
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
BECHADE, ROLAND;FERRAIOLO, FRANK D.;KAUFMANN, BRUCE;NOVOF, ILYA I.;OAKLAND, STEVEN F.;SHAW, KENNETH;SKARSHINSKI, LEON