发明名称 Semiconductor memory with improved sense amplifier layout
摘要 A semiconductor memory has a matrix of memory cells crossed by word lines and bit lines. In each group of eight adjacent bit lines, a first sense amplifier is coupled to the first and sixth bit lines, a second sense amplifier to the third and eighth bit lines, a third sense amplifier to the second and fifth bit lines, and a fourth sense amplifier to the fourth and seventh bit lines. The first and third sense amplifiers are located side by side on one side of the memory matrix, between the second and fifth bit lines. The second and fourth sense amplifiers are located side by side on the opposite side of the memory matrix, between the fourth and seventh bit lines.
申请公布号 US5272665(A) 申请公布日期 1993.12.21
申请号 US19920903258 申请日期 1992.06.24
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 UESUGI, MASARU
分类号 G11C7/18;(IPC1-7):G11C13/00 主分类号 G11C7/18
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